The present invention relates to the field of manufacturing semiconductor devices with patterned metal interconnections, and more particularly, to manufacturing high density semiconductor devices with submicron patterned metal features for local and global interconnections.
Current demands for high density and performance associated with ultra large scale integration require submicron features of about 0.25 microns and under, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require device features manufactured with high precision and uniformity.
Conventional semiconductor devices comprise a substrate and various electrically isolated regions, called active regions, in which individual circuit components, such as transistors comprising gates and source/drain regions, are formed and interconnected. In one interconnection scheme, shown in FIGS. 1(a) and 1(b), source/drain regions 3 and gates 4 of neighboring transistors are connected to one another by local interconnections 5 to form xe2x80x9cstandard cellsxe2x80x9d which, in turn, are connected to each other locally and globally by several patterned metal layers (e.g. 8) interleaved with insulating layers (e.g. 7) formed above and extending substantially horizontally with respect to the substrate 1 surface. The metal layers (e.g. 8) are connected to one another and to the local interconnection 5 by vias (e.g., contacts 6).
Conventional practices employ aluminum alloys for interconnects, with various metals, such as copper, added for electromigration improvement. One conventional interconnect scheme, shown in FIG. 1(a), comprises depositing a composite three-layer metal stack 8 comprising an upper layer 8c of titanium nitride (TiN) or titanium-titanium nitride (Tixe2x80x94TiN), an intermediate layer 8b of aluminum (Al) or Al alloy and a lower layer 8a of titanium (Ti) or Tixe2x80x94TiN, as by sputtering.
A patterned photoresist mask 9 is then formed on the metal layer 8 defining a metal pattern and the underlying metal is etched through the mask 9 to form the pattern of metal lines 8. The quality of the photoresist mask 9 is crucial to the definition of the metal interconnect layer and, ultimately, to device performance. Thus, if defects are observed or detected in the mask, it must be removed and replaced (i.e., reworked) with a defect free mask before etching. A successful resist mask rework completely removes all of the resist 9 without damaging the underlying substrate material, increasing the defect density, or introducing systematic yield variations.
Conventional photoresist mask removal techniques include pumping down the pressure in a plasma chamber after the wafer has been placed on a heated platen and stripping the wafer, such as by oxygen plasma stripping, while the wafer temperature is substantially at the platen temperature of 240xc2x0 C. to 260xc2x0 C. The stripping process is typically followed by solvent cleaning. A new patterned photoresist mask is then formed on the underlying metal layer and etching is conducted to form the patterned metal lines. However, wafers processed by these conventional techniques exhibit an abnormally high defect density after the subsequent metal etch process, due to formation of a residue (R). This residue (R), illustrated in FIG. 1(b), causes bridging between adjacent lines and, hence, short-circuiting and device failure.
Investigation by the inventors revealed that residue (R) was formed as a result of precipitates from an alloy solution, influenced by the temperature and duration of the rework. In one exemplary configuration, copper (Cu) precipitated out of an Aluminum-Copper (Al/1%Cu) alloy at a wafer temperature of about 240xc2x0 C. (roughly corresponding to a platen temperature of about 240xc2x0 C.), leading to residue formation and bridging. It was determined that the residue (R) increased as the concentration of the copper in the AlCu alloy was increased and the residue was found to increase and decrease with increases and decreases in the temperature and duration of the rework.
Generally, a method is needed to permit efficient limitation of wafer temperature during processing to prevent formation of the aforementioned precipitates. More specifically, there is a need for a method enabling replacement of a defective resist mask without the aforementioned bridging yield losses and without collaterally compromising throughput or yield. These needs are particularly acute in manufacturing high density devices having minimal inter-wiring spaces.
The inventors determined that the wafer temperature should be maintained below approximately 210xc2x0 C. to 220xc2x0 C. to prevent residue formation, contrary to conventional plasma strip operations which seek to raise the wafer temperature as high as possible to increase the striprate. One approach to limiting wafer temperature is simply to lower the platen temperature or paddle temperature in the plasma strip chamber. However, the plasma striprate is strongly dependent on the temperature and decreases with decreasing temperature. Thus, merely lowering the platen temperature decreases the striprate and throughput to an undesirable extent.
According to the invention, the earlier stated needs are met in part by a method for manufacturing a semiconductor device including controlling the temperature of a platen or paddle adjacent a wafer to be less than about 210xc2x0 C. The flow rate of an additive to the reactant gases used to create an O2 plasma is controlled to thereby control the resist striprate. A resist layer disposed on the wafer is plasma stripped while maintaining the temperature of the platen or paddle below about 210xc2x0 C. throughout the stripping of the resist layer. Controlling the temperature of the platen or paddle in this manner maintains the wafer temperature below approximately 210xc2x0 C. during the plasma stripping process in accord with the above aspects of the invention and prevents residue (R) formation improving product yield. Controlling the flow rate of the additive to the reactant gases that form the O2 plasma allows a desired striprate to be achieved at temperatures below about 210xc2x0 C.
Additional features and advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only preferred embodiments of the invention are shown and described, simply by way of illustration of the best mode contemplated for carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.